Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 6

1. Thomas Binder, Clemens Heitzinger, Siegfried Selberherr
   A study on global and local optimization techniques for TCAD analysis tasks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:814-822 [Journal]
   
2. Adil Koukab, Kaustav Banerjee, Michel J. Declercq
   Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:823-836 [Journal]
   
3. Shinji Odanaka
   Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:837-842 [Journal]
   
4. Tianhao Zhang, Krishnendu Chakrabarty, Richard B. Fair
   Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:843-858 [Journal]
   
5. Jennifer L. Wong, Farinaz Koushanfar, Seapahn Megerian, Miodrag Potkonjak
   Probabilistic constructive optimization techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:859-868 [Journal]
   
6. Paul D. Kundarewich, Jonathan Rose
   Synthetic circuit generation using clustering and iteration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:869-887 [Journal]
   
7. Olivier Peyran, Zheng Zeng, Wenjun Zhuang
   Area optimization of delay-optimized structures using intrinsic constraint graphs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:888-906 [Journal]
   
8. Sheldon X.-D. Tan, C.-J. Richard Shi
   Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:907-918 [Journal]
   
9. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
   Efficient power profiling for battery-driven embedded system design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:919-932 [Journal]
   
10. Aiman H. El-Maleh, Khaled Al-Utaibi
    An efficient test relaxation technique for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:933-940 [Journal]
    
11. Andrew Labun
    Rapid method to account for process variation in full-chip capacitance extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:941-951 [Journal]
    
12. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Design space exploration for optimizing on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:952-961 [Journal]
    
13. Laurent Latorre, Vincent Beroulle, Pascal Nouet
    Design of CMOS MEMS based on mechanical resonators using a RF simulation approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:962-967 [Journal]
    
14. Jai-Ming Lin, Yao-Wen Chang
    TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:968-980 [Journal]
    
15. Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas
    A unified framework for generating all propagation functions for logic errors and events. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:980-986 [Journal]
    
16. Jennifer L. Wong, Darko Kirovski, Miodrag Potkonjak
    Computational forensic techniques for intellectual property protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:987-994 [Journal]