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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1985, volume: 4, number: 3

  1. Wojciech Maly
    Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:166-177 [Journal]
  2. A. F. Franz, G. A. Franz
    BAMBI -- A Design Model for Power MOSFET's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:177-189 [Journal]
  3. Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh
    Routing Region Definition and Ordering Scheme for Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:189-197 [Journal]
  4. Maciej J. Ciesielski
    Two-Dimensional Routing for the Silc Silicon Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:198-203 [Journal]
  5. Hideaki Kobayashi, Charles E. Drozd
    Efficient Algorithms for Routing Interchangeable Terminals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:204-207 [Journal]
  6. James Reed, Alberto L. Sangiovanni-Vincentelli, Mauro Santomauro
    A New Symbolic Channel Router: YACR2. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:208-219 [Journal]
  7. Omar Wing, Shuo Huang, Rui Wang
    Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:220-231 [Journal]
  8. Fujio Yamamoto, Sakae Takahashi
    Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:232-239 [Journal]
  9. William J. Dally, Randal E. Bryant
    A Hardware Architecture for Switch-Level Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:239-250 [Journal]
  10. Tonysheng Lin, Stephen Y. H. Su
    The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:250-263 [Journal]
  11. Niraj K. Jha, Jacob A. Abraham
    Design of Testable CMOS Logic Circuits Under Arbitrary Delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:264-269 [Journal]
  12. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Optimal State Assignment for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:269-285 [Journal]
  13. Jan M. Rabaey, Stephen P. Pope, Robert W. Brodersen
    An Integrated Automated Layout Generation System for DSP Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:285-296 [Journal]
  14. Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo
    AROMA: An Area Optimized CAD Program for Cascade SC Filter Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:296-303 [Journal]
  15. Hugo De Man, Ivo Bolsens, E. Vanden Meersch, Johan Van Cleynenbreugel
    DIALOG: An Expert Debugging System for MOSVLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:303-311 [Journal]
  16. Prithviraj Banerjee, Jacob A. Abraham
    A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:312-321 [Journal]
  17. Min-Wen Chiang, J. C. Junior, Chuck Kao
    A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:322-328 [Journal]
  18. Masayuki Terai
    A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:329-336 [Journal]
  19. John K. Ousterhout
    A Switch-Level Timing Verifier for Digital MOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:336-349 [Journal]
  20. Di Ma
    A Physical and SPICE-Compatible Model for the MOS Depletion Device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:349-356 [Journal]
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