The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 2

  1. H. Alan Mantooth, Georges G. E. Gielen
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:121-123 [Journal]
  2. Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man
    An analytic Volterra-series-based model for a MEMS variable capacitor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:124-131 [Journal]
  3. Patrick Reynaert, Koen L. R. Mertens, Michiel Steyaert
    A state-space behavioral model for CMOS class E power amplifiers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:132-138 [Journal]
  4. Steven P. Levitan, Jose A. Martinez, Timothy P. Kurzweg, Abhijit Davare, Mark Kahrs, Michael Bails, Donald M. Chiarulli
    System simulation of mixed-signal multi-domain microsystems with piecewise linear models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:139-154 [Journal]
  5. Michal Rewienski, Jacob K. White
    A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:155-170 [Journal]
  6. Joel R. Phillips
    Projection-based approaches for model reduction of weakly nonlinear, time-varying systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:171-187 [Journal]
  7. Alper Demir, Jaijeet S. Roychowdhury
    A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:188-197 [Journal]
  8. Glenn Wolfe, Ranga Vemuri
    Extraction and use of neural network models in automated synthesis of operational amplifiers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:198-212 [Journal]
  9. Bart De Smedt, Georges G. E. Gielen
    WATSON: design space boundary exploration and model generation for analog and RFIC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:213-224 [Journal]
  10. David Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty
    A CAD methodology for optimizing transistor current and sizing in analog CMOS design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:225-237 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002