Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 8

1. Ramesh Karri, Balakrishnan Iyer, Israel Koren
   Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:877-888 [Journal]
   
2. Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana
   Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:889-903 [Journal]
   
3. Kaustav Banerjee, Amit Mehrotra
   Analysis of on-chip inductance effects for distributed RLC interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:904-915 [Journal]
   
4. Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim
   Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:916-927 [Journal]
   
5. Michael D. Hutton, Jonathan Rose, Derek G. Corneil
   Automatic generation of synthetic sequential benchmark circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:928-940 [Journal]
   
6. Michele Favalli, Marcello Dalpasso
   Bridging fault modeling and simulation for deep submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:941-953 [Journal]
   
7. Seongmoon Wang, Sandeep K. Gupta
   An automatic test pattern generator for minimizing switching activity during scan testing activity. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:954-968 [Journal]
   
8. Alexandre César Muniz de Oliveira, Luiz Antonio Nogueira Lorena
   A constructive genetic algorithm for gate matrix layout problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:969-974 [Journal]
   
9. William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Michael A. Driscoll
   BDD minimization by scatter search. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:974-979 [Journal]
   
10. Irith Pomeranz, Sudhakar M. Reddy
    n-pass n-detection fault simulation and its applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:980-986 [Journal]
    
11. Tianhao Zhang, Krishnendu Chakrabarty, Richard B. Fair
    Design of reconfigurable composite microsystems based on hardware/software codesign principles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:987-995 [Journal]