Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1985, volume: 4, number: 1

1. Ting-Hua Chen, Melvin A. Breuer
   Automatic Design for Testability Via Testability Measures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:3-11 [Journal]
   
2. Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada
   CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:12-22 [Journal]
   
3. Susanne E. Hambrusch
   Channel Routing Algorithms for Overlap Models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:23-30 [Journal]
   
4. Thomas G. Szymanski
   Dogleg Channel Routing is NP-Complete. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:31-41 [Journal]
   
5. A. Poncet
   Finite-Element Simulation of Local Oxidation of Silicon. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:41-53 [Journal]
   
6. Jonathan B. Rosenberg
   Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:53-67 [Journal]
   
7. Takao Nishizeki, Nobuji Saito, Kiminobu Suzuki
   A Linear-Time Routing Algorithm for Convex Grids. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:68-76 [Journal]
   
8. Andrzej J. Strojwas, Stephen W. Director
   A Pattern Recognition Based Method for IC Failure Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:76-92 [Journal]
   
9. Alfred E. Dunlop, Brian W. Kernighan
   A Procedure for Placement of Standard-Cell VLSI Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:92-98 [Journal]
   
10. G. Bischoff, J. P. Krusius
    Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:99-110 [Journal]
    
11. A. M. Mazzone
    Three-Dimensional Monte Carlo Simulations--Part II: Recoil Phenomena. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:110-117 [Journal]