Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 10

1. Wim De Pauw
   Multitrees with internal storage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1428-1436 [Journal]
   
2. In-Cheol Park, Chong-Min Kyung
   FAMOS: an efficient scheduling algorithm for high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1437-1448 [Journal]
   
3. Ruchir Puri, Jun Gu
   Microword length minimization in microprogrammed controller synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1449-1457 [Journal]
   
4. Yosinori Watanabe, Robert K. Brayton
   Heuristic minimization of multiple-valued relations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1458-1472 [Journal]
   
5. Steven T. Healey
   An improved model for solving the optimal placement for river-routing problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1473-1480 [Journal]
   
6. Yu Hen Hu, ShaoWei Pan
   SaPOSM: an optimization method applied to parameter extraction of MOSFET models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1481-1487 [Journal]
   
7. Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin
   An adaptive timing-driven placement for high performance VLSIs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1488-1498 [Journal]
   
8. Datong Chen, Satoshi Sugino, Zhiping Yu, Robert W. Dutton
   Modeling of the charge balance condition on floating gates and simulation of EEPROMs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1499-1502 [Journal]
   
9. Ferenc Kovács, Gábor Hosszú
   A proposed method for dynamic fitting of MOS model parameters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1503-1507 [Journal]
   
10. Kenji Harafuji, Akio Misaka, Noboru Nomura, Masahiro Kawamoto, Hirohiko Yamashita
    A novel hierarchical approach for proximity effect correction in electron beam lithography. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1508-1514 [Journal]
    
11. Arlynn W. Smith, Ajeet Rohatgi
    Non-isothermal extension of the Scharfetter-Gummel technique for hot carrier transport in heterostructure simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1515-1523 [Journal]
    
12. Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric Minami, Khandker Quader, Ping K. Ko, Chenming Hu
    Berkeley reliability tools-BERT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1524-1534 [Journal]
    
13. He Yie, Teng Zhimeng
    Nonoscillatory streamline upwind formulations for drift-diffusion equation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1535-1541 [Journal]
    
14. C. Patrick Yue, Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr.
    Improved universal MOSFET electron mobility degradation models for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1542-1546 [Journal]
    
15. Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich
    Clock suppression techniques for synchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1547-1556 [Journal]
    
16. Maria Cristina Vecchi, Massimo Rudan, Giovanni Soncini
    Numerical simulation of optical devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1557-1569 [Journal]
    
17. Jacek Wojciechowski, Jiri Vlach
    Ellipsoidal method for design centering and yield estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1570-1579 [Journal]
    
18. Thyagaraju R. Damarla, Avinash Sathaye
    Applications of one-dimensional cellular automata and linear feedback shift registers for pseudo-exhaustive testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1580-1591 [Journal]
    
19. Lih-Der Chang, Pei-Yung Hsiao, Jin-Tai Yan, Paul-Waie Shew
    A robust over-the-cell channel router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1592-1599 [Journal]
    
20. Kwang-Ting Cheng, Hi-Keung Tony Ma
    On the over-specification problem in sequential ATPG algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1599-1604 [Journal]
    
21. Hideo Fujiwara, Akihiro Yamamoto
    Parity-scan design to reduce the cost of test application. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1604-1611 [Journal]
    
22. Manjote S. Haworth, William P. Birmingham, Daniel E. Haworth
    Optimal part selection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1611-1617 [Journal]
    
23. Olgierd A. Palusinski, Dongjin Lee, Lozios Vakanas
    Comments on `Simulation of lossless symmetrical three conductor systems' by W. Guggenbuhl et al. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1617-1619 [Journal]