Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 1

1. Jong-Yeol Lee, In-Cheol Park
   Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:1-14 [Journal]
   
2. David J. Walkey, Dritan Celo, Tom J. Smy
   A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:15-25 [Journal]
   
3. Nikolay Rubanov
   SubIslands: the probabilistic match assignment algorithm for subcircuit recognition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:26-38 [Journal]
   
4. David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta
   Static electromigration analysis for on-chip signal interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:39-48 [Journal]
   
5. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
   Fast on-chip inductance simulation using a precorrected-FFT method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:49-66 [Journal]
   
6. Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
   Chip-level charged-device modeling and simulation in CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:67-81 [Journal]
   
7. Irith Pomeranz, Sudhakar M. Reddy
   Test enrichment for path delay faults using multiple sets of target faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:82-90 [Journal]
   
8. Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
   Maze routing with buffer insertion under transition time constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:91-95 [Journal]
   
9. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
   Timing constraints for domino logic gates with timing-dependent keepers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:96-103 [Journal]
   
10. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    Automatic interconnection rectification for SoC design verification based on the port order fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:104-114 [Journal]