Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 10

1. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
   Analytical models for crosstalk excitation and propagation in VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1117-1131 [Journal]
   
2. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
   Area fill synthesis for uniform layout density. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1132-1147 [Journal]
   
3. Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
   A multigrid-like technique for power grid analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1148-1160 [Journal]
   
4. Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
   CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1161-1170 [Journal]
   
5. Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty
   Synthesis of single-output space compactors for scan-based sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1171-1179 [Journal]
   
6. David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran
   Slope propagation in static timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1180-1195 [Journal]
   
7. Gregory Wolfe, Jennifer L. Wong, Miodrag Potkonjak
   Watermarking graph partitioning solutions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1196-1204 [Journal]
   
8. Minghorng Lai, Martin D. F. Wong
   Maze routing with buffer insertion and wiresizing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1205-1209 [Journal]
   
9. Rung-Bin Lin
   Comments on "Filling algorithms and analyses for layout density control". [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1209-1211 [Journal]
   
10. Srivaths Ravi, Niraj K. Jha
    Test synthesis of systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1211-1217 [Journal]
    
11. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power profile manipulation: a new approach for reducing test application time under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1217-1225 [Journal]
    
12. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1225-1232 [Journal]