Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 2

1. Marco Saraniti, Achim Rein, Günther Zandler, Peter Vogl, Paolo Lugli
   An efficient multigrid Poisson solver for device simulations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:141-150 [Journal]
   
2. Miodrag Potkonjak, Mani B. Srivastava, Anantha P. Chandrakasan
   Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:151-165 [Journal]
   
3. Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
   Scheduling and control generation with environmental constraints based on automata representations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:166-183 [Journal]
   
4. Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi
   Domain characterization of transmission line models and analyses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:184-193 [Journal]
   
5. Chih-Chuan Lin, Mark E. Law
   2-D mesh adaption and flux discretizations for dopant diffusion modeling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:194-207 [Journal]
   
6. Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng
   A global router with a theoretical bound on the optimal solution. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:208-216 [Journal]
   
7. Hsiao-Feng Steven Chen, D. T. Lee
   A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:217-227 [Journal]
   
8. Sandeep Bhatia, Niraj K. Jha
   Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:228-243 [Journal]
   
9. Yves Blaquière, Michel Dagenais, Yvon Savaria
   Timing analysis speed-up using a hierarchical and a multimode approach. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:244-255 [Journal]
   
10. Y. G. Chen, James B. Kuo
    A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:256-258 [Journal]
    
11. Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz
    A method for area estimation of data-path in high level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:258-265 [Journal]