Sheldon X.-D. Tan, C.-J. Richard Shi Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:401-412 [Journal]
Kenneth L. Shepard, Zhong Tian Return-limited inductances: a practical approach to on-chipinductance extraction. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:425-436 [Journal]
Chauchin Su, Yue-Tsang Chen Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:437-445 [Journal]
Jiang Hu, Sachin S. Sapatnekar Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:446-458 [Journal]
Jue Wu, Elizabeth M. Rudnick Bridge fault diagnosis using stuck-at fault simulation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:489-495 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
