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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 6

  1. Dale E. Hocevar, Paul F. Cox, Ping Yang
    Parametric yield optimization for MOS circuit blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:645-658 [Journal]
  2. Genhong Ruan, Jiri Vlach, James A. Barby
    Current-limited switch-level timing simulator for MOS logic networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:659-667 [Journal]
  3. Bernhard E. Boser, Klaus-Peter Karmann, Horst Martin, Bruce A. Wooley
    Simulating and testing oversampled analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:668-674 [Journal]
  4. Shinji Odanaka, Hiroyuki Umimoto, Mutsuko Wakabayashi, Hideya Esaki
    SMART-P: rigorous three-dimensional process simulator on a supercomputer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:675-683 [Journal]
  5. James P. Cohoon, Patrick L. Heck
    BEAVER: a computational-geometry-based tool for switchbox routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:684-697 [Journal]
  6. Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
    Techniques for multilayer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:698-712 [Journal]
  7. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
    On the verification of sequential machines at differing levels of abstraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:713-722 [Journal]
  8. Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
    Multi-level logic minimization using implicit don't cares. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:723-740 [Journal]
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