Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 1

1. Seiyang Yang, Maciej J. Ciesielski
   Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:4-12 [Journal]
   
2. Srinivas Devadas, A. Richard Newton
   Exact algorithms for output encoding, state assignment, and four-level Boolean minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:13-27 [Journal]
   
3. Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton
   MUSE: a multilevel symbolic encoding algorithm for state assignment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:28-38 [Journal]
   
4. Srinivas Devadas, Kurt Keutzer
   A unified approach to the synthesis of fully testable sequential machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:39-50 [Journal]
   
5. Karen A. Bartlett, Gaetano Borriello, Sitaram Raju
   Timing optimization of multiphase sequential logic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:51-62 [Journal]
   
6. Giovanni De Micheli
   Synchronous logic synthesis: algorithms for cycle-time minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:63-73 [Journal]
   
7. Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Retiming and resynthesis: optimizing sequential networks with combinational techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:74-84 [Journal]
   
8. Raul Camposano
   Path-based scheduling for synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:85-93 [Journal]
   
9. Randal E. Bryant
   Formal verification of memory circuits by switch-level simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:94-102 [Journal]
   
10. Dennis L. Young, Jim Teplik, Harrison D. Weed, Neil T. Tracht, Antonio R. Alvarez
    Application of statistical design and response surface methods to computer-aided VLSI device design II. Desirability functions and Taguchi methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:103-115 [Journal]
    
11. Wing K. Luk, Alvar A. Dean
    Multistack optimization for data-path chip layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:116-129 [Journal]
    
12. Tom Smy, R. Niall Tait, Michael J. Brett
    Ballistic deposition simulation of via metallization using a quasi-three-dimensional model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:130-135 [Journal]
    
13. Niraj K. Jha
    Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:136-143 [Journal]