Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 5

1. Dominik Stoffel, Wolfgang Kunz
   Equivalence checking of arithmetic circuits on the arithmetic bit level. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:586-597 [Journal]
   
2. Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz
   Structural FSM traversal. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:598-619 [Journal]
   
3. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
   Design of high-performance system-on-chips using communication architecture tuners. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:620-636 [Journal]
   
4. Subhasis Bhattacharjee, Dhiraj K. Pradhan
   LPRAM: a novel low-power high-performance RAM design with testability and scalability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:637-651 [Journal]
   
5. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   A hybrid energy-estimation technique for extensible processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:652-664 [Journal]
   
6. Ashish Srivastava, Dennis Sylvester
   Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:665-677 [Journal]
   
7. Luca Daniel, Ong Chin Siong, Sok Chay Low, Kwok Hong Lee, Jacob K. White
   A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:678-693 [Journal]
   
8. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
   Simultaneous floor plan and buffer-block optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:694-703 [Journal]
   
9. Hai Zhou
   Efficient Steiner tree construction based on spanning graphs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:704-710 [Journal]
   
10. Dipak Sitaram, Yu Zheng, Kenneth L. Shepard
    Full-chip, three-dimensional shapes-based RLC extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:711-727 [Journal]
    
11. Martin Fischer, Heinz K. Dirks
    Multigranular parallel algorithms for solving linear equations in VLSI circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:728-736 [Journal]
    
12. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers
    Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:737-757 [Journal]
    
13. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Efficient test solutions for core-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:758-775 [Journal]
    
14. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
    Embedded deterministic test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:776-792 [Journal]
    
15. Yao-Wen Chang, Shih-Ping Lin
    MR: a new framework for multilevel full-chip routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:793-800 [Journal]
    
16. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Testing SoC interconnects for signal integrity using extended JTAG architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:800-811 [Journal]