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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1987, volume: 6, number: 4

  1. Vijay Pitchumani, Qisui Zhang
    A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:497-502 [Journal]
  2. Majid Sarrafzadeh
    Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:503-506 [Journal]
  3. A. Margarino, A. Romano, A. De Gloria, Francesco Curatelli, P. Antognetti
    A Tile-Expansion Router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:507-517 [Journal]
  4. W. K. Luk, Paolo Sipala, Markku Tamminen, Donald T. Tang, Lin S. Woo, Chak-Kuen Wong
    A Hierarchical Global Wiring Algorithm for Custom Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:518-533 [Journal]
  5. Saul A. Kravitz, Rob A. Rutenbar
    Placement by Simulated Annealing on a Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:534-549 [Journal]
  6. Malgorzata Marek-Sadowska
    Pad Assignment for Power Nets in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:550-560 [Journal]
  7. Hossein Modarres, Ronald J. Lomax
    A Formal Approach to Design-Rule Checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:561-573 [Journal]
  8. Philip C. Chan, R. Liu, S. K. Lau, Mario Pinto-Guedes
    A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:574-581 [Journal]
  9. M. C. Hsu, Bing J. Sheu
    Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:582-585 [Journal]
  10. S. L. Wong, C. Andre T. Salama
    Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:586-591 [Journal]
  11. Ihao Chen, Andrzej J. Strojwas
    A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:592-600 [Journal]
  12. Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, Joe D. Rutledge
    HSS--A High-Speed Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:601-617 [Journal]
  13. Randal E. Bryant
    Algorithmic Aspects of Symbolic Switch Network Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:618-633 [Journal]
  14. Randal E. Bryant
    Boolean Analysis of MOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:634-649 [Journal]
  15. Norman P. Jouppi
    Timing Analysis and Performance Improvement of MOS VLSI Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:650-665 [Journal]
  16. Sumit Ghosh
    A Distributed Approach to Timing Verification of Synchronous and Asynchronous Digital Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:666-677 [Journal]
  17. R. J. Bowman, C. C. Brewster
    Determining the Zeros and Poles of Linear Circuit Networks Using Function Approximation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:678-690 [Journal]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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