Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 1

1. Gaetano Borriello, Diederik Verkest, Francky Catthoor
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:1-2 [Journal]
   
2. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
   Local memory exploration and optimization in embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:3-13 [Journal]
   
3. Uwe Eckhardt, Renate Merker
   Hierarchical algorithm partitioning at system level for an improved utilization of memory structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:14-24 [Journal]
   
4. Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
   On the efficiency of formal synthesis-experimental results. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:25-32 [Journal]
   
5. Henning Dierks
   Synthesizing controllers from real-time specifications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:33-43 [Journal]
   
6. Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
   Constraint analysis for DSP code generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:44-57 [Journal]
   
7. Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Durackova
   A new algorithm for elimination of common subexpressions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:58-68 [Journal]
   
8. Frank Vahid
   Techniques for minimizing and balancing I/O during functional partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:69-75 [Journal]