Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 9

1. Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts
   AMGIE-A synthesis environment for CMOS analog integrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1037-1058 [Journal]
   
2. Luca P. Carloni, Kenneth L. McMillan, Alberto L. Sangiovanni-Vincentelli
   Theory of latency-insensitive design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1059-1076 [Journal]
   
3. Jason Cong, Yean-Yow Hwang
   Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1077-1090 [Journal]
   
4. Ki-Wook Kim, Sung-Mo Kang
   Crosstalk noise minimization in domino logic design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1091-1100 [Journal]
   
5. Arlindo L. Oliveira
   Techniques for the creation of digital watermarks in sequentialcircuit designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1101-1117 [Journal]
   
6. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
   Synthesis of power-managed sequential components based oncomputational kernel extraction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1118-1131 [Journal]
   
7. Ismet Bayraktaroglu, Alex Orailoglu
   Concurrent test for digital linear systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1132-1142 [Journal]
   
8. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
   Switching activity generation with automated BIST synthesis forperformance testing of interconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1143-1158 [Journal]
   
9. Shih-Chieh Chang, Zhong-Zhen Wu
   Theorems and extensions of single wire replacement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1159-1164 [Journal]
   
10. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Interconnect sizing and spacing with consideration of couplingcapacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1164-1169 [Journal]
    
11. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    On the complexity of gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1170-1176 [Journal]
    
12. Radomir S. Stankovic, Tsutomu Sasao
    A discussion on the history of research in arithmetic andReed-Muller expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1177-1179 [Journal]