Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 12

1. Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
   Near-optimal critical sink routing tree constructions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1417-1436 [Journal]
   
2. Steven Bova, Graham F. Carey
   A Taylor-Galerkin finite element method for the hydrodynamic semiconductor equations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1437-1444 [Journal]
   
3. Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer
   An integrated system for assigning signal flow directions to CMOS transistors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1445-1458 [Journal]
   
4. Ivan L. Wemple, Andrew T. Yang
   Integrated circuit substrate coupling models based on Voronoi tessellation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1459-1469 [Journal]
   
5. K. Fuchs
   Synthesis for path delay fault testability via tautology-based untestability identification and factorization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1470-1479 [Journal]
   
6. Kamal Chaudhary, Massoud Pedram
   Computing the area versus delay trade-off curves in technology mapping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1480-1489 [Journal]
   
7. Rajmohan Rajaraman, Martin D. F. Wong
   Optimum clustering for delay minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1490-1495 [Journal]
   
8. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
   Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1496-1504 [Journal]
   
9. Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
   NEST: a nonenumerative test generation method for path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1505-1515 [Journal]
   
10. Ted Stanion, Debashis Bhattacharya, Carl Sechen
    An efficient method for generating exhaustive test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1516-1525 [Journal]
    
11. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
    Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1526-1545 [Journal]
    
12. Elizabeth J. Brauer, Sung-Mo Kang
    An algorithm for functional verification of digital ECL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1546-1556 [Journal]
    
13. Kannan Krishna, Stephen W. Director
    The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1557-1568 [Journal]
    
14. Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Synthesis for testability techniques for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1569-1577 [Journal]
    
15. Dhiraj K. Pradhan, Jayashree Saxena
    A novel scheme to reduce test application time in circuits with full scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1577-1586 [Journal]
    
16. Alexander Y. Tetelbaum
    Generalized optimum path search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1586-1590 [Journal]