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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 6

  1. David W. Knapp
    Fasolt: a program for feedback-driven data-path optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:677-695 [Journal]
  2. David C. Ku, Giovanni De Micheli
    Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:696-718 [Journal]
  3. Yung-Ho Shih, Sung-Mo Kang
    Analytic transient solution of general MOS circuit primitives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:719-731 [Journal]
  4. Terence B. Hook
    Automatic extraction of circuit models from layout artwork for a BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:732-738 [Journal]
  5. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
    Provably good performance-driven global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:739-752 [Journal]
  6. Charles R. Bonapace, Chi-Yuan Lo
    An O(n log m) algorithm for VLSI design rule checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:753-758 [Journal]
  7. Joohyun Jin, Jerry G. Fossum
    Non-quasi-static modeling/implementation of BJT current crowding for seminumerical mixed-mode device/circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:759-767 [Journal]
  8. André Ivanov, Yervant Zorian
    Count-based BIST compaction schemes and aliasing probability computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:768-777 [Journal]
  9. Janusz Rajski, Jagadeesh Vasudevamurthy
    The testability-preserving concurrent decomposition and factorization of Boolean expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:778-793 [Journal]
  10. Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
    Testability measures in pseudorandom testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:794-800 [Journal]
  11. Michael J. Bryan, Srinivas Devadas, Kurt Keutzer
    Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:800-803 [Journal]
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