Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 12

1. Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni
   Long and short covering edges in combination logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1245-1253 [Journal]
   
2. Angelo Brambilla, Enrico Dallago
   A circuit-level simulation model of PNPN devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1254-1264 [Journal]
   
3. Jih-Shyr Yih, Pinaki Mazumder
   A neural network design for circuit partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1265-1271 [Journal]
   
4. Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
   Layer assignment for multichip modules. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1272-1277 [Journal]
   
5. Patrick Groeneveld
   A multiple layer contour-based gridless channel router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1278-1288 [Journal]
   
6. Godfried M. Swinkels, Louis J. Hafer
   Schematic generation with an expert system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1289-1306 [Journal]
   
7. Pierre-François Dubois, Alain Puissochet, Anne-Marie Tagant
   A general and flexible switchbox router: CARIOCA. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1307-1317 [Journal]
   
8. Charles Chiang, Majid Sarrafzadeh, Chak-Kuen Wong
   Global routing based on Steiner min-max trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1318-1325 [Journal]
   
9. Gopalakrishnan Vijayan
   Partitioning logic on graph structures to minimize routing cost. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1326-1334 [Journal]
   
10. Gabriel M. Silberman, Ilan Y. Spillinger
    Using functional fault simulation and the difference fault model to estimate implementation fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1335-1343 [Journal]
    
11. Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò
    Aliasing in signature analysis testing with multiple input shift registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1344-1353 [Journal]
    
12. Richard Booth, Marvin White
    Simulation of a MOS transistor with spatially nonuniform channel parameters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1354-1357 [Journal]