Champaka Ramachandran, Fadi J. Kurdahi Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1450-1460 [Journal]
Joe Rodriguez-Tellez, Kahtan A. Mezher, M. Al-Daas Computationally efficient and accurate capacitance model for the GaAs MESFET for microwave nonlinear circuit design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1489-1497 [Journal]
Sanjay L. Manney, Michel S. Nakhla, Qi-Jun Zhang Analysis of nonuniform, frequency-dependent high-speed interconnects using numerical inversion of Laplace transform. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1513-1525 [Journal]
Karl Fuchs, Michael Pabst, Torsten Rössel RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1550-1562 [Journal]