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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 12

  1. Xiaobo Sharon Hu, Steven C. Bass, Ronald G. Harber
    Minimizing the number of delay buffers in the synchronization of pipelined systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1441-1449 [Journal]
  2. Champaka Ramachandran, Fadi J. Kurdahi
    Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1450-1460 [Journal]
  3. Charles Chiang, Chak-Kuen Wong, Majid Sarrafzadeh
    A weighted Steiner tree-based global router with simultaneous length and density minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1461-1469 [Journal]
  4. Massoud Pedram, Bahman S. Nobandegani, Bryan Preas
    Design and analysis of segmented routing channels for row-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1470-1479 [Journal]
  5. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    A general purpose, multiple-way partitioning algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1480-1488 [Journal]
  6. Joe Rodriguez-Tellez, Kahtan A. Mezher, M. Al-Daas
    Computationally efficient and accurate capacitance model for the GaAs MESFET for microwave nonlinear circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1489-1497 [Journal]
  7. Russell Kao, Mark Horowitz
    Timing analysis for piecewise linear Rsim. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1498-1512 [Journal]
  8. Sanjay L. Manney, Michel S. Nakhla, Qi-Jun Zhang
    Analysis of nonuniform, frequency-dependent high-speed interconnects using numerical inversion of Laplace transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1513-1525 [Journal]
  9. Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage
    Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1526-1535 [Journal]
  10. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
    Convexity-based algorithms for design centering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1536-1549 [Journal]
  11. Karl Fuchs, Michael Pabst, Torsten Rössel
    RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1550-1562 [Journal]
  12. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    An edge-based heuristic for Steiner routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1563-1568 [Journal]
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