Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 6

1. Paul E. Landman, Jan M. Rabaey
   Activity-sensitive architectural power analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:571-587 [Journal]
   
2. Mahadevamurty Nemani, Farid N. Najm
   Towards a high-level power estimation capability [digital ICs]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:588-598 [Journal]
   
3. Diana Marculescu, Radu Marculescu, Massoud Pedram
   Information theoretic measures for power analysis [logic design]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:599-610 [Journal]
   
4. Anthony M. Hill, Sung-Mo Kang
   Determining accuracy bounds for simulation-based switching activity estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:611-618 [Journal]
   
5. Sven Wuytack, Francky Catthoor, Hugo De Man
   Transforming set data types to power optimal data structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:619-629 [Journal]
   
6. Luca Benini, Giovanni De Micheli
   Automatic synthesis of low-power gated-clock finite-state machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:630-643 [Journal]
   
7. Christopher K. Lennard, A. Richard Newton
   On estimation accuracy for guiding low-power resynthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:644-664 [Journal]
   
8. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
   Transistor sizing for low power CMOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:665-671 [Journal]
   
9. Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar
   Estimation of energy consumption in speed-independent control circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:672-680 [Journal]
   
10. Chor Ping Low, Hon Wai Leong
    Minimum fault coverage in memory arrays: a fast algorithm and probabilistic analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:681-690 [Journal]
    
11. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
    Post-processing of clock trees via wiresizing and buffering for robust design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:691-701 [Journal]