Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 3

1. Thang Nguyen Bui, Byung Ro Moon
   GRCA: a hybrid genetic algorithm for circuit ratio-cut partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:193-204 [Journal]
   
2. Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng
   Covering conditions and algorithms for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:205-219 [Journal]
   
3. Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli
   Telescopic units: a new paradigm for performance optimization of VLSI designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:220-232 [Journal]
   
4. D. Michael Miller
   An improved method for computing a generalized spectral coefficient. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:233-238 [Journal]
   
5. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
   Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:239-254 [Journal]
   
6. David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson
   Diagnosing realistic bridging faults with single stuck-at information. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:255-268 [Journal]
   
7. Irith Pomeranz, Sudhakar M. Reddy
   Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:269-278 [Journal]
   
8. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
   Sequential logic optimization for low power using input-disabling precomputation architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:279-284 [Journal]