Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 10

1. Clemens Heitzinger, Alireza Sheikholeslami, Jong Mun Park, Siegfried Selberherr
   A method for generating structurally aligned grids for semiconductor device simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1485-1491 [Journal]
   
2. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
   Quasi-static scheduling of independent tasks for reactive systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1492-1514 [Journal]
   
3. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
   Combining ordered best-first search with branch and bound for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1515-1529 [Journal]
   
4. Dongkun Shin, Jihong Kim
   Intra-task voltage scheduling on DVS-enabled hard real-time systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1530-1549 [Journal]
   
5. T. V. Pesic, Nebojsa D. Jankovic
   A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1550-1561 [Journal]
   
6. Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen
   EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1562-1571 [Journal]
   
7. Kenneth Eguro, Scott Hauck
   Resource allocation for coarse-grain FPGA development. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1572-1581 [Journal]
   
8. Soumitra Bose, Amit Nandi
   Schematic array models for associative and non-associative memory circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1582-1593 [Journal]
   
9. Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
   On reducing test application time for scan circuits using limited scan operations and transfer sequences. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1594-1605 [Journal]
   
10. Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas
    Fault diagnosis and logic debugging using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1606-1621 [Journal]
    
11. Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
    An efficient heterogeneous tree multiplexer synthesis technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1622-1629 [Journal]
    
12. Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla
    Evaluating the reliability of NAND multiplexing with PRISM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1629-1637 [Journal]
    
13. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1637-1643 [Journal]