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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 5

  1. Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee
    Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:557-567 [Journal]
  2. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:568-578 [Journal]
  3. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Sequential test generation and synthesis for testability at the register-transfer and logic levels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:579-598 [Journal]
  4. Frederic Mailhot, Giovanni De Micheli
    Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:599-620 [Journal]
  5. Tsutomu Sasao
    EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:621-632 [Journal]
  6. Michael C. McFarland
    Formal verification of sequential hardware: a tutorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:633-654 [Journal]
  7. Liliana Díaz-Olavarrieta, K. Illanko, Safwat G. Zaky
    Goal-oriented decomposition of switching functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:655-665 [Journal]
  8. Hamid Z. Fardi
    Simulation and modeling of p-n-p-n optical switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:666-671 [Journal]
  9. Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
    Stepwise equivalent conductance circuit simulation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:672-683 [Journal]
  10. Wolfgang Kunz, Dhiraj K. Pradhan
    Accelerated dynamic learning for test pattern generation in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:684-694 [Journal]
  11. Adit D. Singh, C. Mani Krishna
    On optimizing VLSI testing for product quality using die-yield prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:695-709 [Journal]
  12. Donald L. Dietmeyer
    Generating minimal covers of symmetric functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:710-713 [Journal]
  13. Martine D. F. Schlag, Pak K. Chan, Jackson Kong
    Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:713-722 [Journal]
  14. Srinivas Devadas
    Comparing two-level and ordered binary decision diagram representations of logic functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:722-723 [Journal]
  15. Jason Cong, Bryan Preas, C. L. Liu
    Physical models and efficient algorithms for over-the-cell routing in standard cell design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:723-734 [Journal]
  16. O. Y. Song, Bong-Hee Park, Premachandran R. Menon
    Divergence and scheduling in functional level concurrent fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:734-736 [Journal]
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