Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 3

1. Donald Chai, Andreas Kuehlmann
   A fast pseudo-Boolean constraint solver. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:305-317 [Journal]
   
2. Satish Pillai, Margarida F. Jacome
   Predicated switching - optimizing speculation on EPIC machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:318-335 [Journal]
   
3. Lin Zhong, Niraj K. Jha
   Interconnect-aware low-power high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:336-351 [Journal]
   
4. Victor Bourenkov, Kevin G. McCarthy, Alan Mathewson
   MOS table models for circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:352-362 [Journal]
   
5. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
   Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:363-381 [Journal]
   
6. Jason Cong, Jie Fang, Min Xie, Yan Zhang
   MARS-a multilevel full-chip gridless routing system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:382-394 [Journal]
   
7. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
   Timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:395-406 [Journal]
   
8. Kai Wang, Malgorzata Marek-Sadowska
   On-chip power-supply network optimization using multigrid-based technique. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:407-417 [Journal]
   
9. Sheldon X.-D. Tan
   A general hierarchical circuit modeling and simulation algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:418-434 [Journal]
   
10. Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski
    Test planning for modular testing of hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:435-448 [Journal]
    
11. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    Built-in sequential fault self-testing of array multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:449-460 [Journal]
    
12. Maged Ghoneima, Yehea I. Ismail
    Optimum positioning of interleaved repeaters in bidirectional buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:461-469 [Journal]
    
13. Suvodeep Gupta, Srinivas Katkoori
    Intrabus crosstalk estimation using word-level statistics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:469-478 [Journal]
    
14. Payam Heydari, Massoud Pedram
    Capacitive coupling noise in high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:478-488 [Journal]
    
15. Spyros Tragoudas, Vijay Nagarandal
    On-chip embedding mechanisms for large sets of vectors for delay test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:488-497 [Journal]