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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1984, volume: 3, number: 3

  1. V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
    A Computational Approach for the Diagnosability of Dynamical Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:165-171 [Journal]
  2. Takeshi Tokuda, Jiro Korematsu, Osamu Tomisawa, S. Asai, I. Ohkura, T. Enomoto
    A Hierarchical Standard Cell Approach for Custom VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:172-177 [Journal]
  3. Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh
    An Efficient Single-Row Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:178-183 [Journal]
  4. Malgorzata Marek-Sadowska
    An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:184-190 [Journal]
  5. J. R. Egan, C. L. Liu
    Bipartite Folding and Partitioning of a PLA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:191-199 [Journal]
  6. John P. Hayes
    Fault Modeling for Digital MOS Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:200-208 [Journal]
  7. F. J. Hill, Zainalabedin Navabi, C. H. Chiang, Duan-Ping Chen, M. Masud
    Hardware Compilation from an RTL to a Storage Logic Array Target. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:208-217 [Journal]
  8. Chung-Kuan Cheng, Ernest S. Kuh
    Module Placement Based on Resistive Network Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:218-225 [Journal]
  9. Ronald A. Rohrer, Hassan Nosrati, Kenneth W. Heizer
    Quasi-Static Control of Explicit Algorithms for Transient Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:226-234 [Journal]
  10. Sangyong Han, Sartaj Sahni
    Single-Row Routing in Narrow Streets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:235-241 [Journal]
  11. John K. Ousterhout
    The User Interface and Implementation of an IC Layout Editor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:242-249 [Journal]
  12. H. N. Brady
    An Approach to Topological Pin Assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:250-255 [Journal]
  13. Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli
    Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:256-256 [Journal]
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