Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 9

1. Luca Benini, Alberto Macii, Massimo Poncino, Riccardo Scarsi
   Architectures and synthesis algorithms for power-efficient businterfaces. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:969-980 [Journal]
   
2. Norman Scheinberg, Aleksey Pinkhasov
   A computer simulation model for simulating distortion in FETresistors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:981-989 [Journal]
   
3. Zheng-Yu Yuan, Zheng-Fan Li, Min-Liu Zou
   Computer-aided analysis of on-chip interconnects near semiconductorsubstrate for high-speed VLSI. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:990-998 [Journal]
   
4. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
   Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:999-1010 [Journal]
   
5. Dirk Stroobandt, Peter Verplaetse, Jan M. Van Campenhout
   Generating synthetic benchmark circuits for evaluating CAD tools. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1011-1022 [Journal]
   
6. Koichi Nose, Takayasu Sakurai
   Analysis and future trend of short-circuit power. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1023-1030 [Journal]
   
7. Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
   A fast signature computation algorithm for LFSR and MISR. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1031-1040 [Journal]
   
8. Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan
   VERILAT: verification using logic augmentation and transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1041-1051 [Journal]
   
9. Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska
   Star test: the theory and its applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1052-1064 [Journal]
   
10. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Improving symbolic reachability analysis by means of activityprofiles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1065-1075 [Journal]
    
11. Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya
    Synthesis of symmetric functions for path-delay fault testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1076-1081 [Journal]
    
12. Craig M. Files, Marek A. Perkowski
    New multivalued functional decomposition algorithms based on MDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1081-1086 [Journal]
    
13. Irith Pomeranz, Sudhakar M. Reddy
    On synchronizable circuits and their synchronizing sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1086-1092 [Journal]