Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 8

1. Ki-Il Kum, Wonyong Sung
   Combined word-length optimization and high-level synthesis ofdigital signal processing systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:921-930 [Journal]
   
2. David L. Rhodes, Wayne Wolf
   RAGS-real-analysis ALAP-guided synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:931-941 [Journal]
   
3. Qing Wu, Qinru Qiu, Massoud Pedram
   Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:942-956 [Journal]
   
4. Angelo Brambilla, Paolo Maffezzoni
   Statistical method for the analysis of interconnects delay insubmicrometer layouts. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:957-966 [Journal]
   
5. Lih-Yang Wang, Yen-Tai Lai
   Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:967-979 [Journal]
   
6. Irith Pomeranz, Y. Zonan
   Testing of scan circuits containing nonisolated random-logic legacycores. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:980-993 [Journal]
   
7. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
   Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:994-1002 [Journal]
   
8. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
   OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:1003-1015 [Journal]
   
9. Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
   Synchronous approach to the functional equivalence of embeddedsystem implementations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:1016-1033 [Journal]