Qing Wu, Qinru Qiu, Massoud Pedram Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:942-956 [Journal]

Angelo Brambilla, Paolo Maffezzoni Statistical method for the analysis of interconnects delay insubmicrometer layouts. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:957-966 [Journal]

Lih-Yang Wang, Yen-Tai Lai Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:967-979 [Journal]

Irith Pomeranz, Y. Zonan Testing of scan circuits containing nonisolated random-logic legacycores. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:980-993 [Journal]

Farzan Fallah, Srinivas Devadas, Kurt Keutzer Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:994-1002 [Journal]

Farzan Fallah, Srinivas Devadas, Kurt Keutzer OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:1003-1015 [Journal]