Daniel Brand Exhaustive simulation need not require an exponential number of tests. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1635-1641 [Journal]
Gabriele Saucier, Pierre Abouzeid Lexicographical expressions of Boolean functions with application to multilevel synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1642-1654 [Journal]
Ingo Schäfer, Marek A. Perkowski Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1655-1664 [Journal]
Chan-Ik Park, Yun-Bo Park An efficient algorithm for VLSI network partitioning problem using a cost function with balancing factor. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1686-1694 [Journal]
Kaushik Roy A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1695-1705 [Journal]
Antonio Gnudi, Davide Ventura, Giorgio Baccarani Modeling impact ionization in a BJT by means of spherical harmonics expansion of the Boltzmann transport equation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1706-1713 [Journal]
Nancy Hitschfeld-Kahler, Paolo Conti, Wolfgang Fichtner Mixed element trees: a generalization of modified octrees for the generation of meshes for the simulation of complex 3-D semiconductor device structures. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1714-1725 [Journal]
M. A. Styblinski, Syed A. Aftab Combination of interpolation and self-organizing approximation techniques-a new approach to circuit performance modeling. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1775-1785 [Journal]
Dong H. Xie, Michel S. Nakhla Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1798-1811 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP