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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 11

  1. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
    An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1621-1634 [Journal]
  2. Daniel Brand
    Exhaustive simulation need not require an exponential number of tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1635-1641 [Journal]
  3. Gabriele Saucier, Pierre Abouzeid
    Lexicographical expressions of Boolean functions with application to multilevel synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1642-1654 [Journal]
  4. Ingo Schäfer, Marek A. Perkowski
    Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1655-1664 [Journal]
  5. Andrew Lumsdaine, Luis Miguel Silveira, Jacob K. White
    Massively parallel simulation algorithms for grid-based analog signal processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1665-1678 [Journal]
  6. Doowon Paik, Sartaj Sahni
    Optimal folding of bit sliced stacks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1679-1685 [Journal]
  7. Chan-Ik Park, Yun-Bo Park
    An efficient algorithm for VLSI network partitioning problem using a cost function with balancing factor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1686-1694 [Journal]
  8. Kaushik Roy
    A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1695-1705 [Journal]
  9. Antonio Gnudi, Davide Ventura, Giorgio Baccarani
    Modeling impact ionization in a BJT by means of spherical harmonics expansion of the Boltzmann transport equation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1706-1713 [Journal]
  10. Nancy Hitschfeld-Kahler, Paolo Conti, Wolfgang Fichtner
    Mixed element trees: a generalization of modified octrees for the generation of meshes for the simulation of complex 3-D semiconductor device structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1714-1725 [Journal]
  11. Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang
    Algorithms for transient three-dimensional mixed-level circuit and device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1726-1733 [Journal]
  12. Peter W. Rambo, Jacques Denavit
    Time stability of Monte Carlo device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1734-1741 [Journal]
  13. Alexei D. Sadovnikov, David J. Roulston
    Quasi-three-dimensional modeling of bipolar transistor characteristics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1742-1748 [Journal]
  14. Motoaki Tanizawa, Mikio Ikeda, Norihiko Kotani, Katsuhiro Tsukamoto, Kazuo Horie
    A complete substrate current model including band-to-band tunneling current for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1749-1757 [Journal]
  15. Tahui Wang, Sheng-Jyh Wu, Chimoon Huang
    Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1758-1761 [Journal]
  16. Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh
    Improving the performance of parallel relaxation-based circuit simulators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1762-1774 [Journal]
  17. M. A. Styblinski, Syed A. Aftab
    Combination of interpolation and self-organizing approximation techniques-a new approach to circuit performance modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1775-1785 [Journal]
  18. Rudi C. Vankemmel, Wim Schoenmaker, Rudi Cartuyvels, Kristin M. De Meyer
    Scaling considerations of the constitutive equations in a 2-D finite element heterojunction simulator PRISM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1786-1797 [Journal]
  19. Dong H. Xie, Michel S. Nakhla
    Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1798-1811 [Journal]
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