Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1987, volume: 6, number: 6

1. Srinivas Devadas, A. Richard Newton
   Topological Optimization of Multiple-Level Array Logic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:915-941 [Journal]
   
2. Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli
   A Detailed Router Based on Incremental Routing Modifications: Mighty. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:942-955 [Journal]
   
3. James P. Cohoon, William D. Paris
   Genetic Placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:956-964 [Journal]
   
4. Ihao Chen, Andrzej J. Strojwas
   Realistic Yield Simulation for VLSIC Structural Failures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:965-980 [Journal]
   
5. Robert F. Lucas, Tom Blank, Jerome J. Tiemann
   A Parallel Solution Method for Large Sparse Systems of Equations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:981-991 [Journal]
   
6. Dundar Dumlugol, Patrick Odent, Johan Cockx, Hugo De Man
   Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:992-1005 [Journal]
   
7. Silvano Gai, Fabio Somenzi, Ernst Ulrich
   Advances in Concurrent Multilevel Simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1006-1012 [Journal]
   
8. Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick
   Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1013-1022 [Journal]
   
9. Joseph E. Hall, Dale E. Hocevar, Ping Yang, Michael J. McGraw
   SPIDER -- A CAD System for Modeling VLSI Metallization Patterns. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1023-1031 [Journal]
   
10. J. Mar, Krish Bhargavan, Steven G. Duvall, Ram Firestone, Dennis J. Lucey, S. N. Nandgaonkar, S. Wu, Kaung-Shia Yu, F. Zarbakhsh
    EASE--An Application-Based CAD System for Process Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1032-1038 [Journal]
    
11. Jacques Benkoski, Andrzej J. Strojwas
    A New Approach to Hierarchical and Statistical Timing Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1039-1052 [Journal]
    
12. Chorng-Yeong Chu, Mark Horowitz
    Charge-Sharing Models for Switch-Level Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1053-1061 [Journal]
    
13. Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
    MIS: A Multiple-Level Logic Optimization System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1062-1081 [Journal]
    
14. Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
    Testability-Driven Random Test-Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1082-1087 [Journal]
    
15. Gabriele Saucier, Michel Crastes de Paulet, P. Sicard
    ASYL: A Rule-Based System for Controller Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1088-1097 [Journal]
    
16. Barry M. Pangrle, Daniel D. Gajski
    Design Tools for Intelligent Silicon Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1098-1112 [Journal]