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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 11

  1. Reinaldo A. Bergamaschi
    SKOL: a system for logic synthesis and technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1342-1355 [Journal]
  2. Robert P. Kurshan, Kenneth L. McMillan
    Analysis of digital circuits through symbolic reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1356-1371 [Journal]
  3. Farid N. Najm, Ibrahim N. Hajj, Ping Yang
    An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1372-1381 [Journal]
  4. Kuo-Feng Liao, Majid Sarrafzadeh
    Boundary single-layer routing with movable terminals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1382-1391 [Journal]
  5. Ioannis G. Tollis
    A new approach to wiring layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1392-1400 [Journal]
  6. Jason Cong
    Pin assignment with global routing for general cell designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1401-1412 [Journal]
  7. Yang Cai, Martin D. F. Wong
    Optimal channel pin assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1413-1424 [Journal]
  8. Martin D. F. Wong, Mohankumar Guruswamy
    Channel ordering for VLSI layout with rectilinear modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1425-1431 [Journal]
  9. Zhong-Yi Zhao, Qi-Ming Zhang, Gen-Lin Tan, J. M. (Jimmy) Xu
    A new preconditioner for CGS iteration in solving large sparse nonsymmetric linear equations in semiconductor device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1432-1440 [Journal]
  10. Craig MacInnes
    The use of small pivot perturbation in circuit analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1441-1446 [Journal]
  11. Keith Nabors, Jacob K. White
    FastCap: a multipole accelerated 3-D capacitance extraction program. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1447-1459 [Journal]
  12. Barry M. Pangrle
    On the complexity of connectivity binding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1460-1465 [Journal]
  13. Jacob Savir, Paul H. Bardell
    Partitioning of polynomial tasks: test generation, an example. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1465-1468 [Journal]
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