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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 12

  1. Zhen-qiu Ning, Patrick Dewilde
    SPIDER: capacitance modelling for VLSI interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1221-1228 [Journal]
  2. Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro
    MOSTSM: a physically based charge conservative MOSFET model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1229-1236 [Journal]
  3. Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen
    Macromodeling CMOS circuits for timing simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1237-1249 [Journal]
  4. Kewal K. Saluja, Rajiv Sharma, Charles R. Kime
    A concurrent testing technique for digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1250-1260 [Journal]
  5. Y. You, John P. Hayes
    Implementation of VLSI self-testing by regularization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1261-1271 [Journal]
  6. Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa
    A macrocell approach for VLSI processor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1272-1277 [Journal]
  7. Yen-Tai Lai, Sany M. Leinwand
    Algorithms for floorplan design via rectangular dualization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1278-1289 [Journal]
  8. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1290-1300 [Journal]
  9. Leo R. Piotrowski
    An improved Spice2 Zener diode model for soft-region simulation capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1301-1303 [Journal]
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