Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1986, volume: 5, number: 3

1. S. Onga, M. Konaka, A. Ohmichi, K. Kanaka, R. Dang
   A Composite Two-Dimensional Process/Device Simulation System (TOPMODE) and its Application for Total Process Designing in Submicron VLSI MOS Device Phase. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:365-370 [Journal]
   
2. J. Katzenelson, E. Weitz
   VLSI Simulation and Data Abstractions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:371-378 [Journal]
   
3. Chia-Jeng Tseng, Daniel P. Siewiorek
   Automated Synthesis of Data Paths in Digital Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:379-395 [Journal]
   
4. Ilan Y. Spillinger, Gabriel M. Silberman
   Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:396-404 [Journal]
   
5. Roger D. Chamberlain, Mark A. Franklin
   Collecting Data About Logic Simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:405-412 [Journal]
   
6. Randy Lee Brown
   Multiple Storage Quad Trees: A Simpler Faster Alternative to Bisector List Quad Trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:413-419 [Journal]
   
7. Robert Michael Owens, Mary Jane Irwin
   A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:420-428 [Journal]
   
8. Gregory J. Fisher, J. Alvin Connelly
   Modeling Time-Dependent Elements for SPICE Transient Analyses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:429-432 [Journal]
   
9. Sun Young Hwang, Robert W. Dutton, Tom Blank
   A Best-First Search Algorithm for Optimal PLA Folding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:433-442 [Journal]
   
10. U. V. Wali, R. N. Pal, B. Chatterjee
    Compact Modified Nodal Approach for Switched-Capacitor Network Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:443-447 [Journal]