Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 1

1. Rolf Drechsler, Bernd Becker
   Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:1-5 [Journal]
   
2. Rohini Gupta, Byron Krauter, Lawrence T. Pileggi
   Transmission line synthesis via constrained multivariable optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:6-19 [Journal]
   
3. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
   Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:20-31 [Journal]
   
4. Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
   Algorithms for an FPGA switch module routing problem with application to global routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:32-46 [Journal]
   
5. Andrew D. Brown, Keith R. Baker, Alan Christopher Williams
   On-line testing of statically and dynamically scheduled synthesized systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:47-57 [Journal]
   
6. Chieh-Yuan Chao, Hung-Jen Lin, L. Miler
   Optimal testing of VLSI analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:58-77 [Journal]
   
7. Ankan K. Pramanick, Sudhakar M. Reddy
   On the fault coverage of gate delay fault detecting tests. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:78-94 [Journal]
   
8. Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi
   The Elmore delay as a bound for RC trees with generalized input signals. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:95-104 [Journal]
   
9. Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
   Incorporating interconnect, register, and clock distribution delays into the retiming process. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:105-120 [Journal]
   
10. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
    Estimation of average switching activity in combinational logic circuits using symbolic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:121-127 [Journal]