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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 3

  1. M. Sytrzycki
    Modeling of gate oxide shorts in MOS transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:193-202 [Journal]
  2. Michael Nicolaidis
    Self-exercising checkers for unified built-in self-test (UBIST). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:203-218 [Journal]
  3. Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara
    An approximation algorithm for the via placement problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:219-228 [Journal]
  4. Ludo Weyten, Wim De Pauw
    Quad list quad trees: a geometrical data structure with improved performance for large region queries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:229-233 [Journal]
  5. Peter Ramyalal Suaris, Gershon Kedem
    A quadrisection-based combined place and route scheme for standard cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:234-244 [Journal]
  6. Ralph-Michael Kling, Prithviraj Banerjee
    ESp: Placement by simulated evolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:245-256 [Journal]
  7. R. Jayakumar, Krishnaiyan Thulasiraman, M. N. S. Swamy
    O(n2) algorithms for graph planarization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:257-267 [Journal]
  8. Michel Dagenais, Nicholas C. Rumin
    On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:268-278 [Journal]
  9. Michael L. Bushnell, Stephen W. Director
    Automated design tool execution in the Ulysses design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:279-287 [Journal]
  10. Wayne Wolf
    How to build a hardware description and measurement system on an object-oriented programming language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:288-301 [Journal]
  11. Evangelos Simoudis
    A knowledge-based system for the evaluation and redesign of digital circuit networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:302-315 [Journal]
  12. El-Sayed A. Talkhan, Aly M. H. Ahmed, Aly E. Salama
    Microprocessors functional testing techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:316-318 [Journal]
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