M. Sytrzycki Modeling of gate oxide shorts in MOS transistors. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:193-202 [Journal]
Michael Nicolaidis Self-exercising checkers for unified built-in self-test (UBIST). [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:203-218 [Journal]
Ludo Weyten, Wim De Pauw Quad list quad trees: a geometrical data structure with improved performance for large region queries. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:229-233 [Journal]
Michel Dagenais, Nicholas C. Rumin On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:268-278 [Journal]
Wayne Wolf How to build a hardware description and measurement system on an object-oriented programming language. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:288-301 [Journal]
Evangelos Simoudis A knowledge-based system for the evaluation and redesign of digital circuit networks. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:302-315 [Journal]