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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 11

  1. Robert Kosik, Peter Fleischmann, Bernhard Haindl, Paola Pietra, Siegfried Selberherr
    On the interplay between meshing and discretization inthree-dimensional diffusion simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1233-1240 [Journal]
  2. Andrea Pacelli, Marco Mastrapasqua, Serge Luryi
    Generation of equivalent circuits from physics-based devicesimulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1241-1250 [Journal]
  3. Shantanu Tarafdar, Miriam Leeser
    A data-centric approach to high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1251-1267 [Journal]
  4. Jason Cong, Songjie Xu
    Performance-driven technology mapping for heterogeneous FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1268-1281 [Journal]
  5. Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini
    Fast and efficient parametric modeling of contact-to-substratecoupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1282-1292 [Journal]
  6. Dingming Xie, Mengzhang Cheng, Leonard Forbes
    SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1293-1303 [Journal]
  7. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Optimal partitioners and end-case placers for standard-cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1304-1313 [Journal]
  8. Joachim Pistorius, Edmée Legai, Michel Minoux
    PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1314-1321 [Journal]
  9. Min Zhao, Sachin S. Sapatnekar
    Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1322-1336 [Journal]
  10. Sachio Hayashi, Masaaki Yamada
    EMI-noise analysis under ASIC design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1337-1346 [Journal]
  11. Mukund Sivaraman, Andrzej J. Strojwas
    Primitive path delay faults: identification and their use in timinganalysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1347-1362 [Journal]
  12. Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
    Estimation of power dissipation using a novel power macromodelingtechnique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1363-1369 [Journal]
  13. Tong Liu, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi
    Testing and testable designs for one-time programmable FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1370-1375 [Journal]
  14. Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams
    BIST hardware synthesis for RTL data paths based on testcompatibility classes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1375-1385 [Journal]
  15. Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
    Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1386-1388 [Journal]
  16. Xiaodong Zhang, Wenlei Shan, Kaushik Roy
    Low-power weighted random pattern testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1389-1398 [Journal]
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