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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 5

  1. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:505-523 [Journal]
  2. Miodrag Potkonjak, Jan M. Rabaey
    Algorithm selection: a quantitative optimization-intensive approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:524-532 [Journal]
  3. Sven Wuytack, Julio Leao da Silva Jr., Francky Catthoor, Gjalt G. de Jong, Chantal Ykman-Couvreur
    Memory management for embedded network applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:533-544 [Journal]
  4. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Improving the efficiency of BDD-based operators by means of partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:545-556 [Journal]
  5. Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas
    A modeling technique for CMOS gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:557-575 [Journal]
  6. J. Joseph Clement, Stefan P. Riege, Radenko Cvijetic, Carl V. Thompson
    Methodology for electromigration critical threshold design rule evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:576-581 [Journal]
  7. Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti
    Parametric yield formulation of MOS IC's affected by mismatch effect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:582-596 [Journal]
  8. Joao Paulo Costa, Mike Chou, Luis Miguel Silveira
    Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:597-607 [Journal]
  9. Chin-Chih Chang, Jason Cong
    An efficient approach to multilayer layer assignment with anapplication to via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:608-620 [Journal]
  10. Srimat T. Chakradhar, Sujit Dey
    Resynthesis and retiming for optimum partial scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:621-630 [Journal]
  11. Laurence Goodby, Alex Orailoglu
    Redundancy and testability in digital filter datapaths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:631-644 [Journal]
  12. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
    Timing verification of sequential dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:645-658 [Journal]
  13. Young-Jun Cha, Chong S. Rim, Kazuo Nakajima
    SEGRA: a very fast general area router for multichip modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:659-665 [Journal]
  14. Irith Pomeranz, Sudhakar M. Reddy
    A comment on "Improving a nonenumerative method to estimate path delay fault coverage". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:665-666 [Journal]
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