Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 6

1. Ruchir Puri, Jun Gu
   An efficient algorithm to search for minimal closed covers in sequential machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:737-745 [Journal]
   
2. Meinhard Paffrath, Karl Steger
   Method of temporary coordinate domains for moving boundary value problems [semiconductor processing simulation]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:746-756 [Journal]
   
3. Yang Cai, Martin D. F. Wong
   On minimizing the number of L-shaped channels in building-block layout [VLSI]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:757-769 [Journal]
   
4. Nobuo Funabiki, Yoshiyasu Takefuji
   A neural network approach to topological via-minimization problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:770-779 [Journal]
   
5. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
   Utilization of vacant terminals for improved over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:780-792 [Journal]
   
6. Kyunrak Chong, Sartaj Sahni
   Optimal realizations of floorplans [VLSI layout]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:793-801 [Journal]
   
7. Thomas Lengauer, Rolf Müller
   Robust and accurate hierarchical floorplanning with integrated global wiring. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:802-809 [Journal]
   
8. Ming-Jiang Zhou, Herbert De Smet, Anita De Bruycker, André Van Calster
   A 2-D boundary element method approach to the simulation of DMOS transistors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:810-816 [Journal]
   
9. Khalid Rahmat, Jacob K. White, Dimitri A. Antoniadis
   Computation of drain and substrate currents in ultra-short-channel nMOSFET's using the hydrodynamic model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:817-824 [Journal]
   
10. Colin C. McAndrew, Bijan K. Bhattacharyya, Omar Wing
    A C_infinity-continuous depletion capacitance model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:825-828 [Journal]
    
11. Lawrence P. Huang, Randal E. Bryant
    Intractability in linear switch-level simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:829-836 [Journal]
    
12. Venkata S. Rangavajjhala, Bharat L. Bhuva, Sherra E. Kerns
    Statistical degradation analysis of digital CMOS IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:837-844 [Journal]
    
13. Peter Saviz, Omar Wing
    Circuit simulation by hierarchical waveform relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:845-860 [Journal]
    
14. Robert C. Melville, Ljiljana Trajkovic, San-Chin Fang, Layne T. Watson
    Artificial parameter homotopy methods for the DC operating point problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:861-877 [Journal]
    
15. Niraj K. Jha, Sying-Jyan Wang
    Design and synthesis of self-checking VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:878-887 [Journal]
    
16. Marcel Jacomet, Walter Guggenbühl
    Layout-dependent fault analysis and test synthesis for CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:888-899 [Journal]
    
17. Neven Orhanovic, Paul Wang, Vijay K. Tripathi
    Time-domain simulation of uniform and nonuniform multiconductor lossy lines by the method of characteristics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:900-904 [Journal]
    
18. Anastasios Vergis
    On the multiple-fault testability of generalized counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:905-909 [Journal]
    
19. Noriyuki Iwamuro, Saburo Tagami
    Two-dimensional power device simulator considering an integral external circuit equation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:909-912 [Journal]