The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 2

  1. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
    Performance-driven interconnection optimization for microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:137-149 [Journal]
  2. Zebo Peng, Krzysztof Kuchcinski
    Automated transformation of algorithms into register-transfer level implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:150-166 [Journal]
  3. June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi, Reily M. Jacoby
    Exact and heuristic algorithms for the minimization of incompletely specified state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:167-177 [Journal]
  4. Yang Cai, Martin D. F. Wong
    On shifting blocks and terminals to minimize channel density. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:178-186 [Journal]
  5. Masayuki Terai, Kazuo Nakajima, Kazuhiro Takahashi, Koji Sato
    A new approach to over-the-cell channel routing with three layers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:187-200 [Journal]
  6. Hans Kosina, Siegfried Selberherr
    A hybrid device simulator that combines Monte Carlo and drift-diffusion analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:201-210 [Journal]
  7. Larry G. Jones, David Blaauw
    A cache-based method for accelerating switch-level simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:211-218 [Journal]
  8. Edward W. Scheckler, Andrew R. Neureuther
    Models and algorithms for three-dimensional topography simulation with SAMPLE-3D. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:219-230 [Journal]
  9. Andrew T. Yang, Yu Liu, Jack T. Yao
    An efficient nonquasi-static diode model for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:231-239 [Journal]
  10. Irith Pomeranz, Sudhakar M. Reddy
    An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:240-250 [Journal]
  11. Irith Pomeranz, Sudhakar M. Reddy
    SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:251-263 [Journal]
  12. Georg Pelz, Uli Roettcher
    Pattern matching and refinement hybrid approach to circuit comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:264-276 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002