Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 11

1. Roberto Guerrieri, Alberto L. Sangiovanni-Vincentelli
   Three-dimensional capacitance evaluation on a Connection Machine. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1125-1133 [Journal]
   
2. David M. Lewis
   Hardware accelerators for timing simulation of VLSI digital circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1134-1149 [Journal]
   
3. Gen-Lin Tan, Shao-Wei Pan, Walter H. Ku, An-Jui Shey
   ADIC-2.C a general-purpose optimization program suitable for integrated circuit design applications using the pseudo objective function substitution method (POSM). [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1150-1163 [Journal]
   
4. Claudio Lombardi, Stefano Manzini, Antonio Saporito, Massimo Vanzi
   A physically based mobility model for numerical simulation of nonplanar devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1164-1171 [Journal]
   
5. Paolo Camurati, P. Gianoglio, R. Gianoglio, Paolo Prinetto
   ESTA: an expert system for DFT rule verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1172-1180 [Journal]
   
6. F. Joel Ferguson, John Paul Shen
   A CMOS fault extractor for inductive fault analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1181-1194 [Journal]
   
7. Jin-fuw Lee
   A new framework of design rules for compaction of VLSI layouts. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1195-1204 [Journal]
   
8. Hwan Gue Cho, C. M. Kyung
   A heuristic standard cell placement algorithm using constrained multistage graph model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1205-1214 [Journal]
   
9. Sharon R. Perkins, Tom Rhyne
   An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1215-1218 [Journal]