Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 9

1. Chuan Lin, Hai Zhou
   Optimal wire retiming without binary search. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1577-1588 [Journal]
   
2. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Application-specific heterogeneous multiprocessor synthesis using extensible processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1589-1602 [Journal]
   
3. Oskar Mencer
   ASC: a stream compiler for computing with FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1603-1617 [Journal]
   
4. Bin Wu, Jianwen Zhu, Farid N. Najm
   Dynamic-range estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1618-1636 [Journal]
   
5. Josep Carmona, José Manuel Colom, Jordi Cortadella, F. García-Vallés
   Synthesis of asynchronous controllers using integer linear programming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1637-1651 [Journal]
   
6. William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski
   Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1652-1663 [Journal]
   
7. Jun Chen, Lei He
   Modeling and synthesis of multiport transmission line for multichannel communication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1664-1676 [Journal]
   
8. B. Lasbouygues, S. Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
   Logical effort model extension to propagation delay representation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1677-1684 [Journal]
   
9. Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
   Analytical yield prediction considering leakage/performance correlation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1685-1695 [Journal]
   
10. Xiangyin Zeng, Jiangqi He, M. N. Abdulla, Qing-Lun Chen
    Understanding and closed-form-formula determination of frequency-dependent bonding-pad characterization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1696-1704 [Journal]
    
11. Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann
    Memory performance prediction for high-performance microprocessors at deep submicrometer technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1705-1718 [Journal]
    
12. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1719-1732 [Journal]
    
13. Prashant Saxena
    On controlling perturbation due to repeaters during quadratic placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1733-1743 [Journal]
    
14. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Minimizing wire length in floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1744-1753 [Journal]
    
15. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    An ECO routing algorithm for eliminating coupling-capacitance violations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1754-1762 [Journal]
    
16. Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
    IC thermal simulation and modeling via efficient multigrid-based approaches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1763-1776 [Journal]
    
17. Hao Gang Wang, Chi Hou Chan, Leung Tsang, Vikram Jandhyala
    On sampling algorithms in multilevel QR factorization method for magnetoquasistatic analysis of integrated circuits over multilayered lossy substrates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1777-1792 [Journal]
    
18. Arijit Mondal, P. P. Chakrabarti
    Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1793-1814 [Journal]
    
19. Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
    Timing analysis for full-custom circuits using symbolic DC formulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1815-1830 [Journal]
    
20. Xiaohua Kong, Radu Negulescu
    Semihiding operators and active-edge specification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1831-1846 [Journal]
    
21. Ruiming Chen, Hai Zhou
    Statistical timing verification for transparently latched circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1847-1855 [Journal]
    
22. Victor De La Luz, Mahmut T. Kandemir, Ibrahim Kolcu
    Reducing memory energy consumption of embedded applications that process dynamically allocated data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1855-1860 [Journal]
    
23. Ruifeng Guo, Srikanth Venkataraman
    An algorithmic technique for diagnosis of faulty scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1861-1868 [Journal]
    
24. Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo
    Analytical bound for unwanted clock skew due to wire width variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1869-1876 [Journal]
    
25. Jens Vygen
    Slack in static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1876-1885 [Journal]