Youssef Saab An improved linear placement algorithm using node compaction. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:952-958 [Journal]

Sachin S. Sapatnekar Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1001-1011 [Journal]

Nobuo Funabiki, Seishi Nishikawa A neural network model for multilayer topological via minimization in a switchbox. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1012-1020 [Journal]

N. F. Rinaldi Fast and simple method for calculating the minority-carrier current in arbitrarily doped semiconductors. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1025-1026 [Journal]

NOTICE1

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NOTICE2

The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP