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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 8

  1. Kwang-Ting Cheng, Hsi-Chuan Chen
    Classification and identification of nonrobust untestable path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:845-853 [Journal]
  2. Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Analysis and synthesis of concurrent digital circuits using control-flow expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:854-876 [Journal]
  3. Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
    Performance optimization using template mapping for datapath-intensive high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:877-888 [Journal]
  4. Sasan Iman, Massoud Pedram
    An approach for multilevel logic optimization targeting low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:889-901 [Journal]
  5. Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi
    Solving the net matching problem in high-performance chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:902-911 [Journal]
  6. Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
    A wire length estimation technique utilizing neighborhood density equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:912-922 [Journal]
  7. Enrico Malavasi, Edoardo Charbon, Eric Felt, Alberto L. Sangiovanni-Vincentelli
    Automation of IC layout with analog constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:923-942 [Journal]
  8. Maurizio Rebaudengo, Matteo Sonza Reorda
    GALLO: a genetic algorithm for floorplan area optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:943-951 [Journal]
  9. Youssef Saab
    An improved linear placement algorithm using node compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:952-958 [Journal]
  10. Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi
    Automatic layout recycling based on layout description and linear programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:959-967 [Journal]
  11. Joe Rodriguez-Tellez, B. P. Stothard, C. Galvan
    Comparison of temperature models for the drain current of MESFET's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:968-976 [Journal]
  12. Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram
    OBDD-based function decomposition: algorithms and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:977-990 [Journal]
  13. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:991-1000 [Journal]
  14. Sachin S. Sapatnekar
    Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1001-1011 [Journal]
  15. Nobuo Funabiki, Seishi Nishikawa
    A neural network model for multilayer topological via minimization in a switchbox. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1012-1020 [Journal]
  16. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
    A weighted random pattern test generation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1020-1025 [Journal]
  17. N. F. Rinaldi
    Fast and simple method for calculating the minority-carrier current in arbitrarily doped semiconductors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:1025-1026 [Journal]
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