Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 12

1. Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo
   An efficient heuristic approach to solve the unate covering problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1377-1388 [Journal]
   
2. Giorgio Casinovi
   Effect of the switching order on power dissipation inswitched-capacitor circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1389-1397 [Journal]
   
3. Johannes Tausch, Junfeng Wang, Jacob K. White
   Improved integral formulations for fast 3-D method-of-momentssolvers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1398-1405 [Journal]
   
4. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
   Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1406-1413 [Journal]
   
5. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
   Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1414-1425 [Journal]
   
6. Ramesh C. Tekumalla, Premachandran R. Menon
   Identification of primitive faults in combinational and sequentialcircuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1426-1442 [Journal]
   
7. Yirng-An Chen, Randal E. Bryant
   An efficient graph representation for arithmetic circuitverification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1443-1454 [Journal]
   
8. Jason Cong, Cheng-Kok Koh, Patrick H. Madden
   Interconnect layout optimization under higher order RLC model forMCM designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1455-1463 [Journal]
   
9. Jie Ding, Krishnendu Chakrabarty, Richard B. Fair
   Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1463-1468 [Journal]
   
10. Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani
    System-level data-format exploration for dynamically allocated datastructures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1469-1472 [Journal]
    
11. Hüseyin Özkaramanli
    A comparison of strong and weak distributed transverse couplingbetween VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1472-1478 [Journal]
    
12. Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp, Paul E. R. Lippens
    Correction to "a two-stage solution approach to multidimensional periodic scheduling". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1479-1479 [Journal]