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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 2

  1. Teng-Sin Pong, Martin A. Brooke
    A parasitics extraction and network reduction algorithm for analog VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:145-149 [Journal]
  2. Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli
    A macromodeling algorithm for analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:150-160 [Journal]
  3. Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki
    A submicrometer MOS transistor I-V model for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:161-170 [Journal]
  4. Peter Feldmann, Tuyen V. Nguyen, Stephen W. Director, Ronald A. Rohrer
    Sensitivity computation in piecewise approximate circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:171-183 [Journal]
  5. Peter M. Maurer
    Scheduling blocks of hierarchical compiled simulation of combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:184-192 [Journal]
  6. Anthony Vannelli
    An adaptation of the interior point method for solving the global routing problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:193-203 [Journal]
  7. Tai-Tsung Ho, S. Sitharama Iyengar, Si-Qing Zheng
    A general greedy channel routing algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:204-211 [Journal]
  8. Uzi Yoeli
    A robust channel router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:212-219 [Journal]
  9. Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio
    Symbolic generation of constrained random logic cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:220-231 [Journal]
  10. Emad Fatemi, Joseph W. Jerome, Stanley Osher
    Solution of the hydrodynamic device model using high-order nonoscillatory shock capturing algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:232-244 [Journal]
  11. J. Gregory Rollins
    Numerical simulator for superconducting integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:245-251 [Journal]
  12. Bruno Ciciani, Giuseppe Iazeolla
    A Markov chain-based yield formula for VLSI fault-tolerant chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:252-259 [Journal]
  13. André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams
    Iterative algorithms for computing aliasing probabilities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:260-265 [Journal]
  14. Michiel M. Ligthart, Rudi J. Stans
    A fault model for PLAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:265-270 [Journal]
  15. Tai-Ching Tuan, Kim-Heng Teo
    On river routing with minimum number of jogs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:271-273 [Journal]
  16. Sarma Sastry, Jen-I Pi
    Estimating the minimum of partitioning and floorplanning problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:273-282 [Journal]
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