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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 3

  1. Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
    Synthesis of high-performance analog circuits in ASTRX/OBLX. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:273-294 [Journal]
  2. Ajoy Opal
    Sampled data simulation of linear and nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:295-307 [Journal]
  3. Chow Sit Tsang-Ping, Christopher M. Snowden, David M. Barry
    A parallel implementation of an electrothermal simulation for GaAs MESFET devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:308-316 [Journal]
  4. Glenn G. Lai, Donald S. Fussell, Martin D. F. Wong
    Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:317-324 [Journal]
  5. Kevin Cattell, Jon C. Muzio
    Synthesis of one-dimensional linear hybrid cellular automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:325-335 [Journal]
  6. Jin-Tai Yan, Pei-Yung Hsiao
    Minimizing the number of switchboxes for region definition and ordering assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:336-347 [Journal]
  7. Guy Even, Ilan Y. Spillinger, Leon Stok
    Retiming revisited and reversed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:348-357 [Journal]
  8. Cheng-Hsi Chen, Ioannis G. Tollis
    An Omega(k2) lower bound for area optimization of spiral floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:358-360 [Journal]
  9. Razak Hossain, Menghui Zheng, Alexander Albicki
    Reducing power dissipation in CMOS circuits by signal probability based transistor reordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:361-368 [Journal]
  10. Ogan Ocah, Mehmet Ali Tan, Abdullah Atalar
    A new method for nonlinear circuit simulation in time domain: NOWE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:368-374 [Journal]
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