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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 8

  1. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    A region-based theory for state assignment in speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:793-812 [Journal]
  2. Eric Lehman, Yosinatori Watanabe, Joel Grodstein, Heather Harkness
    Logic decomposition during technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:813-834 [Journal]
  3. Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin
    Externally hazard-free implementations of asynchronous control circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:835-848 [Journal]
  4. Scott Hauck, Gaetano Borriello
    An evaluation of bipartitioning techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:849-866 [Journal]
  5. Noel Menezes, Ross Baldick, Lawrence T. Pileggi
    A sequential quadratic programming approach to concurrent gate and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:867-881 [Journal]
  6. Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang
    iTEM: a temperature-dependent electromigration reliability diagnosis tool. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:882-893 [Journal]
  7. Peter A. Walker, Sumit Ghosh
    On the nature and inadequacies of transport timing delay constructs in VHDL descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:894-915 [Journal]
  8. Krishnendu Chakrabarty, John P. Hayes
    On the quality of accumulator-based compaction of test responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:916-922 [Journal]
  9. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
    Compact test sets for high defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:923-930 [Journal]
  10. S. Yu, B. W. Jervis, Kevin R. Eckersall, Ian M. Bell
    Diagnosis of CMOS op-amps with gate oxide short faults using multilayer perceptrons. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:930-935 [Journal]
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