Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 11

1. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
   On variable clock methods for path delay testing of sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1237-1249 [Journal]
   
2. Ming Qu, M. A. Styblinski
   Parameter extraction for statistical IC modeling based on recursive inverse approximation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1250-1259 [Journal]
   
3. Anand Raghunathan, Niraj K. Jha
   SCALP: an iterative-improvement-based low-power data path synthesis system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1260-1277 [Journal]
   
4. Maurizio Damiani
   The state reduction of nondeterministic finite-state machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1278-1291 [Journal]
   
5. Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano
   Partitioning and analysis of static digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1292-1310 [Journal]
   
6. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Theory and algorithms for state minimization of nondeterministic FSMs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1311-1322 [Journal]
   
7. Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
   TIGER: an efficient timing-driven global router for gate array and standard cell layout design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1323-1331 [Journal]
   
8. Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
   A delay budgeting algorithm ensuring maximum flexibility in placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1332-1341 [Journal]
   
9. Wern-Jieh Sun, Carl Sechen
   A parallel standard cell placement algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1342-1357 [Journal]
   
10. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self-test for DSP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1358-1369 [Journal]
    
11. Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
    Redundancy removal and test generation for circuits with non-Boolean primitives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1370-1377 [Journal]
    
12. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
    Design of minimum and uniform bipartites for optimum connection blocks of FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1377-1383 [Journal]
    
13. C. S. Murthy, M. Gall
    Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1383-1389 [Journal]