Görschwin Fey, Rolf Drechsler Minimizing the number of paths in BDDs: Theory and algorithm. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:4-11 [Journal]

Wenjian Yu, Mengsheng Zhang, Zeyi Wang Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:12-18 [Journal]

Jaewon Seo, Taewhan Kim, Joonwon Lee Optimal intratask dynamic voltage-scaling technique and its practical extensions. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:47-57 [Journal]

Arijit Raychowdhury, Kaushik Roy Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:58-65 [Journal]

Jaijeet S. Roychowdhury, Robert C. Melville Delivering global DC convergence for large mixed-signal circuits via homotopy/continuation methods. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:66-78 [Journal]

Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:79-91 [Journal]

Li Shang, Li-Shiuan Peh, Niraj K. Jha PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:92-110 [Journal]

Ying Zhang, Krishnendu Chakrabarty A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:111-125 [Journal]

Imad A. Ferzli, Farid N. Najm Analysis and verification of power grids considering process-induced leakage-current variations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:126-143 [Journal]