Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 1

1. Görschwin Fey, Rolf Drechsler
   Minimizing the number of paths in BDDs: Theory and algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:4-11 [Journal]
   
2. Wenjian Yu, Mengsheng Zhang, Zeyi Wang
   Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:12-18 [Journal]
   
3. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
   Micropreemption synthesis: an enabling mechanism for multitask VLSI systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:19-30 [Journal]
   
4. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
   Bitwise scheduling to balance the computational cost of behavioral specifications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:31-46 [Journal]
   
5. Jaewon Seo, Taewhan Kim, Joonwon Lee
   Optimal intratask dynamic voltage-scaling technique and its practical extensions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:47-57 [Journal]
   
6. Arijit Raychowdhury, Kaushik Roy
   Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:58-65 [Journal]
   
7. Jaijeet S. Roychowdhury, Robert C. Melville
   Delivering global DC convergence for large mixed-signal circuits via homotopy/continuation methods. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:66-78 [Journal]
   
8. Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee
   Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:79-91 [Journal]
   
9. Li Shang, Li-Shiuan Peh, Niraj K. Jha
   PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:92-110 [Journal]
   
10. Ying Zhang, Krishnendu Chakrabarty
    A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:111-125 [Journal]
    
11. Imad A. Ferzli, Farid N. Najm
    Analysis and verification of power grids considering process-induced leakage-current variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:126-143 [Journal]
    
12. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Optimal placement of power-supply pads and pins. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:144-154 [Journal]
    
13. Quming Zhou, Kartik Mohanram
    Gate sizing to radiation harden combinational logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:155-166 [Journal]
    
14. Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov
    Fast detection of data retention faults and other SRAM cell open defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:167-180 [Journal]
    
15. Qiang Xu, Nicola Nicolici
    Multifrequency TAM design for hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:181-196 [Journal]
    
16. Shih-yu Yang, Christos A. Papachristou
    A method for detecting interconnect DSM defects in systems on chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:197-204 [Journal]