Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 9

1. Tiziano Villa, Alberto L. Sangiovanni-Vincentelli
   NOVA: state assignment of finite state machines for optimal two-level logic implementation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:905-924 [Journal]
   
2. Gert Goossens, Jan M. Rabaey, Joos Vandewalle, Hugo De Man
   An efficient microcode compiler for application specific DSP processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:925-937 [Journal]
   
3. Michael C. McFarland, Thaddeus J. Kowalski
   Incorporating bottom-up design into hardware synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:938-950 [Journal]
   
4. Resve A. Saleh, Jacob K. White
   Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:951-958 [Journal]
   
5. Bill Lin, A. Richard Newton
   A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:959-969 [Journal]
   
6. Matthias F. M. Stallmann, Thomas A. Hughes, Wentai Liu
   Unconstrained via minimization for topological multilayer routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:970-980 [Journal]
   
7. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
   Toward massively parallel automatic test generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:981-994 [Journal]
   
8. Farid N. Najm, Ibrahim N. Hajj
   The complexity of fault detection in MOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:995-1001 [Journal]
   
9. Chung-Yu Wu, Ming-Chuen Shiau
   Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:1002-1009 [Journal]
   
10. F. Joel Ferguson
    Detection of multiple faults in MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:1009-1014 [Journal]