Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 6

1. Sundarar Mohan, Jian Ping Sun, Pinaki Mazumder, George I. Haddad
   Device and circuit simulation of quantum electronic devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:653-662 [Journal]
   
2. Ing-Jer Huang, Alvin M. Despain
   Synthesis of application specific instruction sets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:663-675 [Journal]
   
3. Mani B. Srivastava, Robert W. Brodersen
   SIERA: a unified framework for rapid-prototyping of system-level hardware and software. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:676-693 [Journal]
   
4. Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
   SpecCharts: a VHDL front-end for embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:694-706 [Journal]
   
5. Akira Onozawa, Kamal Chaudhary, Ernest S. Kuh
   Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:707-719 [Journal]
   
6. Karl Michael Eickhoff, Walter L. Engl
   Levelized incomplete LU factorization and its application to large-scale circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:720-727 [Journal]
   
7. Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal
   Energy models for delay testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:728-739 [Journal]
   
8. Yih-Lang Li, Cheng-Wen Wu
   Cellular automata for efficient parallel logic and fault simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:740-749 [Journal]
   
9. Sridhar Narayanan, Melvin A. Breuer
   Reconfiguration techniques for a single scan chain. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:750-765 [Journal]
   
10. T. W. Her, Martin D. F. Wong
    On over-the-cell channel routing with cell orientations consideration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:766-772 [Journal]
    
11. Wuudiann Ke, Premachandran R. Menon
    Delay-testable implementations of symmetric functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:772-775 [Journal]
    
12. Venkat Thanvantri, Sartaj Sahni
    Folding a stack of equal width components. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:775-780 [Journal]
    
13. Bernard A. McCoy, Gabriel Robins
    Non-tree routing [VLSI layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:780-784 [Journal]